10/8/2021 0 Comments Mw.Dsk Emulator Os-9 68K -Mac
The ZPU Evo on FPGA fabric or the K64F.V1.0 of the tranZPUter had design restrictions which in all honesty make the project much harder to complete, for example, because of my lack of experience soldering BGA (Ball Grid Array)IC's, I chose the next best thing, a pre-fab FPGA board, the CYC1000 with the FPGA already soldered. It should also run independent of the controlling IO processor, ie. The tranZPUter and tranZPUter SW are actively being developed and changes are reflected in the documentation on a regular basis.The tranZPUter SW is an offshoot from the tranZPUter project and utilises a Freescale K64F processor as the IO Control processor as opposed to the ZPU in the original tranZPUter project.During testing of the tranZPUter v1.0 and with the advent of the RFS v2.0 upgrade with CP/M it was noticed that the tranZPUter should be updated so that the Z80 had additional memoryAnd was able to run at higher clock frequencies. :) The content of each post is copyrighted on the date of publication by the respective contributor and is protected under the Copyright Laws of the United States of America, Canada, the Commonwealth of Australia, the United Kingdom and other international treaties.
![]() Mw.Dsk Emulator Os-9 68K - Software Written ForThe C/C++ control software written for the tranZPUter SW is intended to work on the tranZPUter under the ZPU.As the design replaces a Z80 in-situ it is not limited to the MZ80A but can be used in any Z80 based computer with the right software adaptations, ie. This is all made possible with bus masteringWhere the original CPU is tri-stated and the K64F takes control of the bus and the underlying original mainboard peripherals, when needed.The upgrade also extends the Z80 hardware capabilities by providing additional RAM to allow for a 64K version of CP/M and to increase the speed of the processor whilst maintaining theOriginal speed when accessing the Sharp MZ80A motherboard peripherals.This design is a work in progress, working in tandem with the tranZPUter. A software Emulator could be writtenTo prolong the usage of the software but there is something special about using original hardware and this is an alternative to keep the machine original yet provide an upgrade that can powerThe machine with additional processing capabilities, storage and with multiple different CPU's based in software like the PiCoPro on the BBC Micro. Besides being part of history, it has a software base that is useful from time to time and still has followers.The benefitsOf using a soft CPU is potentially better performance albeit this is yet to be determined as the K64F only runs at 120MHz. There is no real need to use the MZ80A memory when using a soft CPU. The program memory could either be that on the MZ80A or the faster K64F memory. The project adds the suffix SW for *S*oft*W*are to distinguishTo provide different CPU's it is just a matter of taking existing CPU emulators, for example those used in the PiCoPro and adapting them to use the CPU signals on the MZ80A bus via thisDesigns interface. It uses a Freescale K64F ARM Cortex-M4 in place of theZPU Evo as the tranZPUter SW is more a software solution to the requirement rather than the ZPU Evo which is based on VHDL on an FPGA. The ZPU Evo provides the intended Menu, SD, Video Overlay services to theSharp MZ80A by tri-stating the original Z80 and accessing the MZ80A memory and peripherals as though they were ZPU devices.The tranZPUter SW follows on from the tranZPUter design in it's goals and makes an improvement on the underlying Z80 hardware at the same time.It is also used where a soft processor completely idle's the hard Z80 and acts as the main computer CPU. The device taking control of the Z80 bus could transfer data muchFaster than the Z80 running a program to perform the same action, hence the benefit.Bus mastering is used to take control of the Z80 bus and to transfer data between main memory and an SD Card or between the I/O processor and the Video displayBuffer for presentation of menu's. Bus mastering was typically usedBy devices such as DMA for fast transfer of data from an I/O device to memory, or memory to memory for applications such as video/graphics. The ability to switch the Z80 out of circuit and control the remaining computer hardware as required. Higher CPU performance will be a benefit toPrograms such as CP/M or databases such as DBase II.In the gallery are pictures of the current design and files uploaded onto github are relatively stable, WIP files wont be uploaded as they are in constant flux.The basics of this design lie in Z80 bus mastering, ie.![]() ![]() Mapping blocks of the underlying Sharp MZ80A address space out and mapping in blocks of the 512Kbyte static RAM), a programmable decoder in the form of a Flash RAM is used. As the design needs to be flexible at this stage on memory remapping(ie. Imagine, a 6809 or a 68000The design centres around lifting the original Z80 onto a daughter card and rerouting several of its signals such that they can be controlled as needed.In order to be able to run programs for other Sharp models (ie.MZ-700) or 64K CP/M the design adds a 512KB Static RAM device with necessary paging logic. A future version 2 will see the removal of all discrete logic and the 512KB Flash RAM decoder and be replaced with a CPLD.// Structure to contain inter CPU communications memory for command service processing and results. Version 1.1 will also use more SMD devices to shrink the PCB size such that itWill fit inside the casing of the MZ-80A, MZ-80B and MZ-700. The design fully works now and version 1.1 will see logic reduction as far as possible but keep the use of discrete logic rather than a GAL/PAL. The above revision, 1.0d adds extra logic which on the prototype PCB is realised with p-p wiring and piggybackIC's. If the RFS board has been installed then an update to the RFS software will make use of the additional enhanced hardware features.If the RFS board has not been installed and you add the IO Control processor (a Teensy 3.5) then a whole new range of options becomes available which match and exceed those available with the RFS board.Using this design it will be easier to use an FPGA in place of the Teensy 3.5 for the final tranZPUter project.As the project has progressed small changes have been made to the first cut PCB to reflect fixes and enhancements. This struct // exists in both the z80 and K64F domains and data is sync'd between them as needed.
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